1. Field of the Invention
Generally, the present invention relates to sophisticated integrated circuits, and, more particularly, to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
For many device technology generations, the gate structures of most transistor elements have comprised silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate dielectric layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices have turned to gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths of 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide or silicon oxynitride and polysilicon (polySiON) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate dielectric layer of an HK/MG gate structure. For example, in some transistor element designs, a high-k gate dielectric layer may include hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like, as well as any one of several combinations thereof, as may be required by the overall design parameters of the device. Furthermore, a metal material layer made up of one or more of a plurality of different non-polysilicon metal gate electrode materials may be formed above the high-k gate dielectric layer in HK/MG configurations so as to control the work function of the transistor, which is sometimes referred to as a work-function material, or a work-function material layer. These work-function materials may include, for example, titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
In recent years, an overall improvement in semiconductor device performance has been realized based on the use of HK/MG gate electrode configurations. However, a decrease in the reliability of HK/MG devices may sometimes occur as a result of various processing-induced defects, such as point defects, e.g., dangling bonds and the like, that may be present in the high-k dielectric bulk material, or at the interface between the high-k dielectric layer and the underlying interfacial silicon dioxide or silicon oxynitride layer. In some instances, these point defects can lead to a decrease in the time dependent dielectric breakdown (TDDB) of the device, or to an increase in bias temperature instability (BTI), either of which may result in a decrease in the overall reliability of HK/MG devices.
One prior art method that has been used to at least incrementally address the defect-related reliability problems described above is by increasing the thickness of the high-k dielectric layer, increasing the thickness of the interfacial layer or increasing the thickness of both layers. However, it should be noted that simply increasing the thicknesses of the high-k dielectric layer and/or interfacial layer has somewhat limited benefits in many device applications, as some device parameters, such as, for example, threshold voltage, device performance and the like, may be detrimentally affected by the increased thicknesses. Accordingly, this approach is typically only utilized when the equivalent oxide thickness (EOT) adjustments of the interfacial layer plus high-k film thickness do not exceed approximately 0.2 Å, as the detrimental effects associated with an increased EOT of more than about 0.2 Å may outweigh the incremental benefits it may otherwise provide.
Another prior art approach that has been used to address the point defect problems associated with high-k dielectric layers as described above is to perform an implantation process to implant ions of a chemical element, such as fluorine and the like, that is known to passivate point defects in and around high-k dielectric layers of the type that may be created during HK/MG device processing. FIGS. 1a-1d depict some illustrative prior art implantation processes, which are generally described below.
FIG. 1a schematically illustrates a semiconductor device 100 in an early manufacturing stage of, for example, a gate-first technique for forming HK/MG transistor elements, wherein an insulating portion of a gate electrode material stack has been formed in advance of forming a layer of gate electrode material and patterning the material stack to form a gate structure. The semiconductor device 100 of FIG. 1a includes a substrate 101 and a semiconductor layer 102 formed thereabove. The semiconductor device 100 also includes an interfacial layer 103 that has been formed on the semiconductor layer 102, which may be on the order of 4-6 Å thick, and which may be made up of, for example, silicon dioxide or silicon oxynitride. A high-k dielectric layer 104 having thickness of approximately 1-2 nm and comprising, for example, hafnium oxide has also been formed above the interfacial layer 103.
FIG. 1b schematically illustrates a close-up view of the semiconductor device 100, and more specifically, the close-up view in the area of the interfacial layer 103 and the high-k dielectric layer 104. As shown in FIG. 1b, point defects 104p may be present in the high-k dielectric layer 104 and/or near an interface 103f between the interfacial layer 103 and the high-k dielectric layer 104.
During the manufacturing stage illustrated in FIGS. 1a and 1b, an implantation process 120 is performed to implant, for example, fluorine ions, into the high-k dielectric layer 104 so as to passivate the point defects 104p. However, due to the fact that the high-k dielectric layer 104 is very thin, e.g., on the order of 1-2 nm as noted above, relatively low implantation energies would generally be necessary to appropriately adjust the position of the implanted ions in such a thin layer. As such, it can be difficult to control the implantation process 120 in such a manner so as to obtain a consistent ion density throughout, or a specific position within, the high-k dielectric layer 104. Accordingly, the implantation process 120 may not readily lend itself to the typical production environment, as it may not always provide a precisely repeatable, and therefore reliable, passivation treatment of the point defects 104p. 
FIG. 1c schematically illustrates another prior art process that has been used for passivating the point defects 104p that is similar to that illustrated in FIGS. 1a-1b, as described above. However, as shown in FIG. 1c, a sacrificial layer 112 has been formed above the high-k dielectric layer 104 prior to performing an implantation process 121 that is used to implant, for example, fluorine ions, into the high-k dielectric layer 104. The sacrificial layer 112 may be any suitable material that can be selectively removed with respect to the high-k dielectric layer 104 during a later manufacturing stage, such as a metal material or polysilicon, and the like. Depending on the implantation energy used during the implantation process 121, controllability of the ion density in and around the area of the high-k dielectric layer may be enhanced to some degree when compared to the implantation process 120 described with respect to FIG. 1b above. However, precise control and repeatability of the overall implantation process, and therefore overall device reliability, may still be difficult to achieve. Moreover, the use of a sacrificial layer 112 will generally tend to increase process integration complexity (and therefore device cost) due to the additional processing steps that are required first to deposit the layer 112, and then to remove the layer 112 prior to forming the remaining layers of the HK/MG gate material stack.
FIG. 1d schematically illustrates yet another prior art implantation process, wherein a semiconductor device 100 is in a substantially advanced manufacturing stage as compared to methods illustrated in FIGS. 1a-1c above. As shown in FIG. 1 d, a gate patterning process has been performed so as to form a gate structure 110 that includes the interfacial layer 103, the high-k gate dielectric layer 104 and a gate electrode 105 above the semiconductor layer 102. In a so-called “gate first” approach, the gate electrode 105 may be, for example, a metal gate electrode, and may include, as appropriate, a work-function material layer as described above, whereas, in a so-called “gate last” approach, the gate electrode 105 may be, for example, polysilicon. In many process integration schemes, after the gate structure 110 has been formed, an implantation sequence is generally performed so as to form source and drain regions (not shown) of the device in the semiconductor layer 102 adjacent to the sidewalls of the gate structure 110. Depending on the overall device requirements, sidewall spacers (not shown) may be formed on or adjacent to the sidewalls of the gate structure 110 prior to and/or during the implantation sequence.
As shown in FIG. 1d, the implantation sequence that is used to form the source and drain regions of the semiconductor device 100 is adjusted to include a tilt-angle implantation process 122 that is designed to implant, for example, fluorine ions so as to passivate any point defects 104p as previously described. However, in many cases, due to the masking or shielding effect of the gate electrode 105, the region 110r of the gate structure 110 into which the ions are implanted during the tilt-angle implantation process 122 may be limited, e.g., to a distance 110L, such that only the edge regions 104e of the high-k dielectric layer 104 may be effectively passivated. As such, the implantation method illustrated in FIG. 1c generally has limited application to those devices having gate lengths and/or gate widths that are within certain dimensional limitations, such as on the order of approximately 10-30 nm.
Accordingly, there is a need to develop processing techniques that are adapted to passivating point defects that may be formed in and around the high-k gate dielectric layer and interfacial layer of HK/MG devices. The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.